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general description the MAX1535 is a highly integrated, multichemistry bat- tery charger that simplifies construction of advanced smart chargers with a minimum number of external com- ponents. it uses intel? system management bus (smbus) to control the charge voltage, charge current, and the maximum current drawn from the ac adapter. high efficiency is achieved through use of a constant off- time step-down topology with synchronous rectification. in addition to support of the smart battery charger specifications rev 1.1, the MAX1535 includes addition- al features. the maximum current drawn from the ac adapter is programmable to avoid overloads when sup- plying the load and the battery charger simultaneously. this enables the user to reduce the cost of the ac adapter. the MAX1535 provides a digital output that indicates the presence of an ac adapter. based on the presence or absence of the ac adapter, the MAX1535 automatically selects the appropriate source for supply- ing power to the system by controlling two external p- channel mosfets. under system control, the MAX1535 allows the battery to undergo a relearning or condition- ing cycle in which the battery is completely discharged through the system load and then recharged. the MAX1535 is capable of charging 2, 3, or 4 lithium- ion (li+) cells in series, providing charge currents as high as 8a. the dc-to-dc converter in the MAX1535 uses a high-side p-channel switch with an n-channel synchronous rectifier. the charge current and input cur- rent-limit sense amplifiers have low input-offset errors and can use small-value sense resistors (0.01 ? , typ). the MAX1535 is available in a 5mm x 5mm 32-pin thin qfn package and operates over the extended -40? to +85? temperature range. an evaluation kit is available to reduce design time. applications notebook and subnotebook computers tablet pcs portable equipment with rechargeable batteries features compliant with level 2 smart battery charger specifications rev 1.1 intel smbus 2-wire serial interface ?.5% charge-voltage accuracy 11-bit charge-voltage resolution ?% input current-limit accuracy uses small (10m ? ) current-sense resistors 8a maximum charge current 6-bit input and charge-current resolution 8v to 28v input voltage range 175s charge safety timer automatic selection of system power source charges any battery chemistry (li+, nicd, nimh, lead acid, etc.) MAX1535 highly integrated level 2 smbus battery charger ________________________________________________________________ maxim integrated products 1 17 i.c. 18 gnd 19 batt 20 csin 21 csip 22 pgnd 23 dlo 24 dlov top view 9 vmax 10 imax 11 dac 12 v dd 13 thm 14 sda 15 scl 16 1 dcin 2 ldo 3 acin 4 ref 5 gnd 6 ccs 7 cci 8 ccv 25 dhiv 26 dhi 27 src 28 cssn 29 cssp 30 pdl 31 pds 32 acok int MAX1535 thin qfn (5mm x 5mm) pin configuration ordering information 19-2848; rev 0; 4/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package MAX1535etj -40 c to +85 c 32 thin qfn (5mm x 5mm)
MAX1535 highly integrated level 2 smbus battery charger 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dcin, cssp, cssn, src, acok to gnd .............-0.3v to +30v dhiv to src .............................................................-6v to +0.3v dhi, pdl, pds to gnd ...............................-0.3v to v src + 0.3v batt, csip, csin to gnd .....................................-0.3v to +20v csip to csin, or cssp to cssn ...........................-0.3v to +0.3v cci, ccs, ccv, dac, ref to gnd ............-0.3v to v ldo + 0.3v v dd , acin, scl, sda, dlov, ldo, thm, int , imax, vmax to gnd...........................................................-0.3v to +6v dlov to ldo.........................................................-0.3v to +0.3v dlo to pgnd............................................-0.3v to v dlov + 0.3v pgnd to gnd .......................................................-0.3v to +0.3v ldo short-circuit current...................................................50ma continuous power dissipation (t a = +70 c) 32-pin thin qfn (derate 21.3mw/ c above +70 c) ...1702mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-60 c to +150 c lead temperature (soldering, 10s) .................................+300 c electrical characteristics (circuit of figure 1. v dcin = v cssp = v cssn = 18v, v batt = v csip = v csin = 12v, v dd = 3.3v, acin = pgnd = gnd, ldo = dlov, vmax = imax = ref, c ldo = 1f, c dhiv = 0.1f, c ref = 1f, t a = 0? to +85? . typical values are at t a = +25 c, unless other- wise noted.) parameter conditions min typ max units charge-voltage regulation chargevoltage() = 0x41a0 and 0x3130 -0.5 +0.5 chargevoltage() = 0x20d0 -0.8 +0.8 charge-voltage accuracy chargevoltage() = 0x1060 -1.0 +1.0 % chargevoltage() = 0x41a0 16.716 16.800 16.884 chargevoltage() = 0x3130 12.529 12.592 12.655 chargevoltage() = 0x20d0 8.332 8.400 8.468 full-charge voltage chargevoltage() = 0x1060 4.150 4.192 4.234 v charge-current regulation csip-to-csin full-scale current- sense voltage v batt = 12v 76.60 80.64 84.67 mv compliance current accuracy 10m ? sense resistor (r2 in figure 1) between csip and csin; chargecurrent() = 0x1f80 -5 +5 % 10m ? sense resistor (r2 in figure 1) between csip and csin; chargecurrent() = 0x1f80 7.660 8.064 8.467 a charge current 10m ? sense resistor (r2 in figure 1) between csip and csin; chargecurrent() = 0x0080 128 ma batt/csip/csin input voltage range 0 19 v v dcin = 0v, or charger not switching 0.1 1.0 csip/csin input current v csip = v csin = 12v 300 700 a input-current regulation cssp-to-cssn full-scale current-sense voltage v dcin = 18v 104.5 110.0 115.5 mv
MAX1535 highly integrated level 2 smbus battery charger _______________________________________________________________________________________ 3 parameter conditions min typ max units 10m ? sense resistor (r1 in figure 1) between cssp and cssn; inputcurrent() = 0x1580 (11.008a) -5 +5 10m ? sense resistor (r1 in figure 1) between cssp and cssn; inputcurrent() = 0x1000 (8.192a) -3 +3 10m ? sense resistor (r1 in figure 1) between cssp and cssn; inputcurrent() = 0x0800 (4.096a) -6.5 +6.5 % input current-limit accuracy por (inputcurrent() = 0x0080) 256 ma cssp/cssn input voltage range 8 28 v v dcin = 0v 0.1 1.0 cssp/cssn input current v cssp = v cssn = v dcin > 8.0v 300 750 a supply and linear regulator dcin input voltage range 8 28 v dcin falling 7.0 7.4 dcin undervoltage lockout trip point dcin rising 7.50 7.85 v dcin quiescent current 8v < v dcin < 28v 2.7 6.0 ma v batt = 19v, v dcin = 0v, or charger not switching 0.1 1.0 batt input current v batt = 2v to 19v, v dcin > v batt + 0.3v 200 500 a ldo output voltage 8v < v dcin < 28v, no load 5.25 5.40 5.50 v ldo load regulation 0 < i ldo < 10ma 34 100 mv ldo undervoltage lockout trip point v dcin = 8v 3.20 4.00 5.15 v v dd range 2.7 5.5 v v dd uvlo rising threshold 2.5 2.7 v v dd uvlo hysteresis 100 mv v dd quiescent current v dcin < 6v, v dd = 5.5v, v scl = v sda = 5.5v 17 27 a reference ref output voltage 0 < i ref < 500a 4.083 4.096 4.109 v ref undervoltage lockout trip point ref falling 3.1 3.9 v trip points batt power_fail threshold v dcin falling 50 100 150 mv batt power_fail threshold hysteresis 100 200 300 mv acin threshold acin rising 1.966 2.048 2.130 v acin threshold hysteresis 10 20 30 mv acin input bias current v acin = 2.048v -1 +1 a electrical characteristics (continued) (circuit of figure 1. v dcin = v cssp = v cssn = 18v, v batt = v csip = v csin = 12v, v dd = 3.3v, acin = pgnd = gnd, ldo = dlov, vmax = imax = ref, c ldo = 1f, c dhiv = 0.1f, c ref = 1f, t a = 0 c to +85 c . typical values are at t a = +25 c, unless other- wise noted.)
MAX1535 highly integrated level 2 smbus battery charger 4 _______________________________________________________________________________________ parameter conditions min typ max units switching regulator v batt = 16.8v, v dcin = 20v 360 400 440 off-time v batt = 19.2v, v dcin = 19.5v 270 300 340 ns dlov supply current chargermode() = 0x0001 5 10 a maximum discontinuous mode peak current 0.5 a battery undervoltage charge current v batt = 2.6v per cell 128 ma dhiv output voltage with respect to src -4.5 -5.0 -5.5 v dhiv sink current 10 ma dhi on-resistance low v dhi = v dhiv , i dhi = -10ma 4 7 ? dhi on-resistance high v dhi = v src , i dhi = 10ma 1 3 ? dlo on-resistance high v dlov = 4.5v, i dlo = 100ma 4 7 ? dlo on-resistance low v dlov = 4.5v, i dlo = -100ma 1 3 ? error amplifiers gmv transconductance chargevoltage () = 0x41a0, v batt = 16.8v 0.0625 0.1250 0.2500 a/mv gmi transconductance chargecurrent () = 0x1f80, v csip - v csin = 80.64mv 0.5 1 2 a/mv gms transconductance inputcurrent () = 0x1580, v cssp - v cssn = 110.08mv 0.5 1 2 a/mv cci clamp voltage 0.25v < v cci < 2.0v 150 300 600 mv ccv clamp voltage 0.25v < v ccv < 2.0v 150 300 600 mv ccs clamp voltage 0.25v < v ccs < 2.0v 150 300 600 mv acok acok input voltage range 0 28 v acok sink current v acok = 0.4v, acin = 2.5v 1 ma acok leakage current v acok = 28v, acin = 1.5v 1 a pds, pdl switch control pds switch turn-off threshold dcin with respect to batt, dcin falling 50 100 150 mv pdl switch turn-on threshold dcin with respect to batt, dcin falling 50 100 150 mv pds switch threshold hysteresis dcin with respect to batt 200 mv pdl switch threshold hysteresis dcin with respect to batt 200 mv pds output low voltage, pds below src i pds = 0v 8 10 12 v pds turn-on current pds = src 6 12 ma pds turn-off current v pds = v src - 2v, v dcin = 16v 10 50 ma pdl turn-on resistance pdl = gnd 50 100 150 k ? pdl turn-off current v cssn - v pdl = 1.5v 6 12 ma pdl and pds transition delay time pds and pdl are unloaded 4 10 15 s electrical characteristics (continued) (circuit of figure 1. v dcin = v cssp = v cssn = 18v, v batt = v csip = v csin = 12v, v dd = 3.3v, acin = pgnd = gnd, ldo = dlov, vmax = imax = ref, c ldo = 1f, c dhiv = 0.1f, c ref = 1f, t a = 0 c to +85 c . typical values are at t a = +25 c, unless other- wise noted.)
MAX1535 highly integrated level 2 smbus battery charger _______________________________________________________________________________________ 5 parameter conditions min typ max units pdl-to-pds switchover time in relearn mode pds and pdl are unloaded 4 10 16 s maximum charge-voltage setting v batt to v vmax ratio 4.5 5.0 5.5 v/v v max input voltage range 0 v ref v v max input bias current 0 < v vmax < v ref 1 a maximum charge-current setting i charge to v imax ratio 4 5 6 a/v imax input voltage range 0 v ref v imax input bias current 0 < v imax < v ref 1 a thermistor comparator thermistor overrange threshold v dd = 2.7v to 5.5v, thm falling 89.5 91 92.5 % of v d d thermistor cold threshold v dd = 2.7v to 5.5v, thm falling 73.5 75 76.5 % of v d d thermistor hot threshold v dd = 2.7v to 5.5v, thm falling 21.5 23 24.5 % of v d d thermistor underrange threshold v dd = 2.7v to 5.5v, thm falling 3.5 5 6.5 % of v dd thermistor comparator hysteresis all four comparators, v dd = 2.7v to 5.5v 50 mv smbus interface level specifications (v dd = 2.7v to 5.5v) sda/scl input low voltage v dd = 2.7v to 5.5v 0.8 v sda/scl input high voltage v dd = 2.7v to 5.5v 2.1 v sda/scl input bias current v dd = 2.7v to 5.5v -1 +1 a sda, int output sink current vsda = 0.4v 6 ma int output high leakage current v int = 5.5v 1 a int output low voltage i int = 1ma 25 200 mv smbus timing specifications (v dd = 2.7v to 5.5v) smbus frequency 10 100 khz smbus free time 4.7 s start condition setup time from scl 4 s start condition hold time from scl 4.7 s stop condition setup time from scl 4 s sda hold time from scl 300 ns sda setup time from scl 250 ns scl low timeout (note 1) 25 35 ms electrical characteristics (continued) (circuit of figure 1. v dcin = v cssp = v cssn = 18v, v batt = v csip = v csin = 12v, v dd = 3.3v, acin = pgnd = gnd, ldo = dlov, vmax = imax = ref, c ldo = 1f, c dhiv = 0.1f, c ref = 1f, t a = 0 c to +85 c . typical values are at t a = +25 c, unless other- wise noted.)
MAX1535 highly integrated level 2 smbus battery charger 6 _______________________________________________________________________________________ parameter conditions min typ max units scl low period 4.7 s scl high period 4 s maximum charging period without a chargevoltage() or chargecurrent() command 140 175 210 s electrical characteristics (continued) (circuit of figure 1. v dcin = v cssp = v cssn = 18v, v batt = v csip = v csin = 12v, v dd = 3.3v, acin = pgnd = gnd, ldo = dlov, vmax = imax = ref, c ldo = 1f, c dhiv = 0.1f, c ref = 1f, t a = 0 c to +85 c . typical values are at t a = +25 c, unless other- wise noted.) parameter conditions min typ max units charge-voltage regulation chargevoltage() = 0x41a0 and 0x3130 -1.6 +1.6 chargevoltage() = 0x20d0 -1.6 +1.6 charge-voltage accuracy chargevoltage() = 0x1060 -1.8 +1.8 % chargevoltage() = 0x41a0 16.532 17.068 chargevoltage() = 0x3130 12.390 12.794 chargevoltage() = 0x20d0 8.266 8.534 full-charge voltage chargevoltage() = 0x1060 4.116 4.268 v charge-current regulation csip-to-csin full-scale current- sense voltage v batt = 12v 72.58 88.70 mv compliance current accuracy 10m ? sense resistor (r2 in figure 1) between csip and csin; chargecurrent() = 0x1f80 -10 +10 % charge current 10m ? sense resistor (r2 in figure 1) between csip and csin; chargecurrent() = 0x1f80 7.258 8.870 a batt/csip/csin input voltage range 0 19 v csip/csin input current v csip = v csin = 12v 800 a input-current regulation cssp-to-cssn full-scale current-sense voltage v dcin = 18v 99 121 mv 10m ? sense resistor (r1 in figure 1) between cssp and cssn; inputcurrent() = 0x1580 (11.008a) -10 +10 10m ? sense resistor (r1 in figure 1) between cssp and cssn; inputcurrent() = 0x1000 (8.192a) -8 +8 input current-limit accuracy 10m ? sense resistor (r1 in figure 1) between cssp and cssn; inputcurrent() = 0x0800 (4.096a) -10 +10 % electrical characteristics (circuit of figure 1. v dcin = v cssp = v cssn = 18v, v batt = v csip = v csin = 12v, v dd = 3.3v, acin = pgnd = gnd, ldo = dlov, vmax = imax = ref, c ldo = 1f, c dhiv = 0.1f, c ref = 1f, t a = -40 c to +85 c , unless otherwise noted.) (note 2)
MAX1535 highly integrated level 2 smbus battery charger _______________________________________________________________________________________ 7 parameter conditions min typ max units cssp/cssn input voltage range 8 28 v cssp/cssn input current v cssp = v cssn = v dcin > 8.0v 800 a supply and linear regulator dcin input voltage range 8 28 v dcin falling 7.0 dcin undervoltage lockout trip point dcin rising 7.85 v dcin quiescent current 8v < v dcin < 28v 8 ma batt input current v batt = 2v to 19v, v dcin > v batt + 0.3v 800 a ldo output voltage 8v < v dcin < 28v, no load 5.15 5.65 v ldo load regulation 0 < i ldo < 10ma 100 mv ldo undervoltage lockout trip point v dcin = 8v 3.00 5.35 v v dd range 2.7 5.5 v v dd quiescent current v dcin < 6v, v dd = 5.5v, v scl = v sda = 5.5v 27 a reference ref output voltage 0 < i ref < 500a 4.035 4.157 v ref undervoltage lockout trip point ref falling 3.9 v trip points batt power_fail threshold v dcin falling 60 160 mv batt power_fail threshold hysteresis 90 310 mv acin threshold acin rising 1.966 2.129 v acin threshold hysteresis 5 35 mv switching regulator v batt = 16.8v, v dcin = 20v 360 440 off-time v batt = 19.2v, v dcin = 19.5v 270 340 ns dlov supply current chargermode() = 0x0001 10 a battery undervoltage charge current v batt = 2.6v per cell 64 192 ma dhiv output voltage with respect to src -4.4 -5.5 v dhiv sink current 10 ma dhi on-resistance low v dhi = v dhiv , i dhi = -10ma 7 ? dhi on-resistance high v dhi = v src , i dhi = 10ma 3 ? dlo on-resistance high v dlov = 4.5v, i dlo = 100ma 7 ? dlo on-resistance low v dlov = 4.5v, i dlo = -100ma 3 ? error amplifiers gmv transconductance chargevoltage() = 0x41a0, v batt = 16.8v 0.0625 0.2500 a/mv electrical characteristics (continued) (circuit of figure 1. v dcin = v cssp = v cssn = 18v, v batt = v csip = v csin = 12v, v dd = 3.3v, acin = pgnd = gnd, ldo = dlov, vmax = imax = ref, c ldo = 1f, c dhiv = 0.1f, c ref = 1f, t a = -40 c to +85 c , unless otherwise noted.) (note 2)
MAX1535 highly integrated level 2 smbus battery charger 8 _______________________________________________________________________________________ parameter conditions min typ max units gmi transconductance chargecurrent() = 0x1f80, v csip - v csin = 80.64mv 0.5 2 a/mv gms transconductance inputcurrent() = 0x1580, v cssp - v cssn = 110.08mv 0.5 2 a/mv cci clamp voltage 0.25v < v cci < 2.0v 140 600 mv ccv clamp voltage 0.25v < v ccv < 2.0v 140 600 mv ccs clamp voltage 0.25v < v ccs < 2.0v 140 600 mv acok acok input voltage range 0 28 v acok sink current v acok = 0.4v, acin = 2.5v 1 ma pds, pdl switch control pds switch turn-off threshold dcin with respect to batt, dcin falling 40 160 mv pdl switch turn-on threshold dcin with respect to batt, dcin falling 40 160 mv pds output low voltage, pds below src i pds = 0 8 12 v pds turn-on current pds = src 6 ma pds turn-off current v pds = v src - 2v, v dcin = 16v 10 ma pdl turn-on resistance pdl = gnd 40 160 k ? pdl turn-off current v cssn - v pdl = 1.5v 6 ma pdl and pds transition delay time pds and pdl are unloaded 4 15 s pdl-to-pds switchover time in relearn mode pds and pdl are unloaded 4 16 s maximum charge-voltage setting vmax input voltage range 0 v ref v vmax to v batt ratio 0 < v vmax < v ref 4.5 5.5 v/v maximum charge-current setting imax input voltage range 0 v ref v imax to i charge ratio 0 < v imax < v ref 4 6 a/v thermistor comparator thermistor overrange threshold v dd = 2.7v to 5.5v, thm falling 89.5 92.5 % of v dd thermistor cold threshold v dd = 2.7v to 5.5v, thm falling 73.5 76.5 % of v dd thermistor hot threshold v dd = 2.7v to 5.5v, thm falling 21.5 24.5 % of v dd thermistor underrange threshold v dd = 2.7v to 5.5v, thm falling 3.5 6.5 % of v dd smbus interface level specifications (v dd = 2.7v to 5.5v) sda/scl input low voltage v dd = 2.7v to 5.5v 0.8 v sda/scl input high voltage v dd = 2.7v to 5.5v 2.15 v sda, int output sink current vsda = 0.4v 6 ma int output low voltage i int = 1ma 200 mv electrical characteristics (continued) (circuit of figure 1. v dcin = v cssp = v cssn = 18v, v batt = v csip = v csin = 12v, v dd = 3.3v, acin = pgnd = gnd, ldo = dlov, vmax = imax = ref, c ldo = 1f, c dhiv = 0.1f, c ref = 1f, t a = -40 c to +85 c , unless otherwise noted.) (note 2)
MAX1535 highly integrated level 2 smbus battery charger _______________________________________________________________________________________ 9 parameter conditions min typ max units smbus timing specifications (v dd = 2.7v to 5.5v) smbus frequency 10 100 khz smbus free time 4.7 s start condition setup time from scl 4 s start condition hold time from scl 4.7 s stop condition setup time from scl 4 s sda hold time from scl 300 ns sda setup time from scl 250 ns scl low timeout (note 1) 25 35 ms scl low period 4.7 s scl high period 4 s maximum charging period without a chargevoltage() or chargecurrent() command 130 220 s electrical characteristics (continued) (circuit of figure 1. v dcin = v cssp = v cssn = 18v, v batt = v csip = v csin = 12v, v dd = 3.3v, acin = pgnd = gnd, ldo = dlov, vmax = imax = ref, c ldo = 1f, c dhiv = 0.1f, c ref = 1f, t a = -40 c to +85 c , unless otherwise noted.) (note 2) note 1: devices participating in a transfer time out when any clock low exceeds the 25ms minimum timeout period. devices that have detected a timeout condition must reset the communication no later than the 35ms maximum timeout period. both a master and a slave must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms). note 2: specifications to -40 c are guaranteed by design, not production tested.
MAX1535 highly integrated level 2 smbus battery charger 10 ______________________________________________________________________________________ typical operating characteristics (circuit of figure 1, v dcin = 20v, t a = +25 c, unless otherwise noted.) transient response (battery removal and insertion) MAX1535 toc01 4ms/div a: battery voltage, 500mv/div, ac-coupled b: v ccv , 500mv/div c: v cci , 500mv/div d: charge current, 2a/div a 0v d 0v 16.8vdc c b c b c b batt inserted batt removed load switch control (adapter insertion) MAX1535 toc02 200 s/div d 0v 0v 0v 0v c b a a: adapter input voltage, 20v/div b: v cssn , 20v/div c: v pds , 20v/div d: v pdl , 20v/div system load transient MAX1535 toc03 400 s/div 0v e 0v f d 0v a a: v batt , 500mv/div, ac-coupled b: v ccs , 500mv/div c: v cci , 500mv/div d: ac adapter current, 5a/div e: system load, 5a/div f: charge current, 5a/div c b c c b b ldo load regulation (v in = 20v) MAX1535 toc04 ldo current (ma) ldo voltage error (%) 8 6 4 2 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 -1.0 010 ldo line regulation MAX1535 toc05 input voltage (v) ldo voltage error (%) 24 20 16 12 -0.008 -0.006 -0.004 -0.002 0 0.002 0.004 0.006 0.008 0.010 -0.010 828 ref load regulation MAX1535 toc06 ref load current ( a) ref voltage error (%) 400 300 200 100 -0.08 -0.06 -0.04 -0.02 0 -0.10 0 500 efficiency vs. charge current (constant-voltage mode) MAX1535 toc08 charge current (a) efficiency (%) 6 4 2 50 60 70 80 90 100 40 08 v charge = 8.4v v charge = 12.6v v charge = 16.8v ref voltage error vs. temperature MAX1535 toc10 temperature ( c) ref voltage error (%) 80 60 40 20 0 -20 -0.08 -0.06 -0.04 -0.02 0 0.02 -0.10 -40 100
MAX1535 highly integrated level 2 smbus battery charger ______________________________________________________________________________________ 11 frequency vs. v in - v batt MAX1535 toc10 v in - v batt (v) frequency (khz) 16 12 8 4 100 200 300 400 500 600 0 020 charge-voltage accuracy MAX1535 toc11 chargevoltage() code (v) charge voltage error (%) 16 12 8 -0.5 0 0.5 1.0 -1.0 420 charge-current accuracy MAX1535 toc12 chargecurrent() setting (a) charge-current error (%) 6 4 2 -2.5 0 2.5 5.0 -5.0 08 input-current accuracy MAX1535 toc13 inputcurrent() setting (a) input current error (%) 10 8 6 4 2 -5.0 -2.5 0 2.5 -7.5 012 typical operating characteristics (continued) (circuit of figure 1, v dcin = 20v, t a = +25 c, unless otherwise noted.) efficiency vs. charge current (constant-current mode) MAX1535 toc09 charge current (a) efficiency (%) 6 4 2 50 60 70 80 90 100 40 08 v charge = 8.4v v charge = 12.6v v charge = 16.8v input/charge current vs. system load current MAX1535 toc14 system load current (a) input/charge current (a) 6 4 2 2 4 6 8 0 08 chargecurrent() = 4a inputcurrent() = 6a input current charge current maximum charge voltage vs. imax MAX1535 toc15 imax voltage (v) maximum charge voltage (v) 4 3 2 1 2 4 6 8 10 0 05 slope 5v/v maximum charge current vs. vmax MAX1535 toc16 vmax voltage (v) maximum charge current (a) 4 3 2 1 4 8 12 16 20 0 05 slope 5a/v
MAX1535 highly integrated level 2 smbus battery charger 12 ______________________________________________________________________________________ pin description pin name function 1 dcin dc supply voltage input. bypass dcin to power ground (pgnd) with a 1f ceramic capacitor. 2 ldo 5.4v li near - reg ul ator outp ut. the l i near r eg ul ator p ow er s the i nter nal ci r cui tr y of the d evi ce. the i np ut of the l i near r eg ul ator i s sup p l i ed fr om d c in . byp ass ld o w i th a 1f cer am i c cap aci tor to gn d . 3 acin ac adapter detect input. this uncommitted comparator input can be used to detect if the ac adapter voltage is available for charging. 4 ref 4.096v (typical) reference voltage output. bypass ref with a 1f ceramic capacitor to gnd. 5 gnd analog ground 6 ccs input current-limit regulation loop compensation point. connect a 0.01f capacitor to gnd. 7 cci charge-current regulation loop compensation point. connect a 0.01f capacitor to gnd. 8 ccv charge-voltage regulation loop compensation point. connect a 20k ? resistor in series with a 0.01f capacitor to gnd. 9 vmax analog control input for setting the maximum charge voltage. the maximum charge voltage can never go above the limit set by vmax. the ratio of maximum charge voltage to vmax voltage is 5v/v. 10 imax analog control input for setting the maximum charge current. the maximum charge current can never go above the limit set by imax. the ratio of maximum charge current to imax voltage is 5a/v. 11 dac dac voltage output. bypass dac with a 0.1f ceramic capacitor to gnd. 12 v dd logic circuitry supply voltage input. the voltage range of v dd is 2.7v to 5.5v. 13 thm thermistor voltage input 14 sda smbus data input/output. sda is an open-drain output. an external pullup resistor is needed. 15 scl smbus clock input. an external pullup resistor is needed. 16 int interrupt output. int is an open-drain output. an external pullup resistor is needed. 17 i.c. internally connected pin. leave it unconnected or connect it to ground. 18 gnd analog ground 19 batt battery voltage input 20 csin negative input to the charge current-sense amplifier 21 csip positive input to the charge current-sense amplifier. connect a 10m ? current-sense resistor from csip to csin. 22 pgnd power ground 23 dlo low-side power mosfet gate driver output. connect dlo to the gate of the low-side n-channel mosfet. 24 dlov low-side gate driver supply. bypass dlov with a 0.1f ceramic capacitor to pgnd. 25 dhiv high-side gate driver supply. bypass dhiv with a 0.1f ceramic capacitor to cssn. 26 dhi high-side power mosfet gate driver output. connect dhi to the gate of the high-side p-channel mosfet. 27 src source connection for pds and pdl switch drivers 28 cssn negative input to the input current-limit sense amplifier 29 cssp positive input to the input current-limit sense amplifier. connect a 10m ? current-sense resistor from cssp to cssn. 30 pdl system load p-channel mosfet switch driver output. when the MAX1535 is powered down, the pdl output is pulled to ground through an internal 100k ? resistor. 31 pds power source p-channel mosfet switch driver output. when the MAX1535 is powered down, the pds output is pulled to src through an internal 1m ? resistor. 32 acok ac detect output. this high-voltage open-drain output is low impedance when acin is greater than ref/2. the acok output remains high impedance when the MAX1535 is powered down.
MAX1535 highly integrated level 2 smbus battery charger ______________________________________________________________________________________ 13 detailed description the MAX1535 includes all the functions necessary to charge li+, nimh, and nicd smart batteries. a high- efficiency, synchronous-rectified, step-down dc-to-dc converter is used to implement a precision constant- current, constant-voltage charger with input current lim- iting. the dc-to-dc converter uses an external p-chan- nel mosfet as the buck switch and an external n-channel mosfet as the synchronous rectifier to con- vert the input voltage to the required charge current and voltage. the charge current and input current-limit sense amplifiers have low input-offset errors and can use small-value sense resistors. the MAX1535 features a voltage-regulation loop (ccv) and two current-regulation loops (cci and ccs). the loops operate independently of each other. the ccv voltage-regulation loop monitors batt to ensure that its voltage never exceeds the voltage set by the chargevoltage() command. the cci battery current- regulation loop monitors current delivered to batt to ensure that it never exceeds the current limit set by the chargecurrent() command. the charge current-regula- tion loop is in control as long as the batt voltage is below the set point. when the batt voltage reaches its set point, the voltage-regulation loop takes control and maintains the battery voltage at the set point. a third loop (ccs) takes control and reduces the charge cur- rent when the sum of the system load and the input cur- rent to the charger exceeds the power-source current limit set by the inputcurrent() command. the MAX1535 also allows the user to clamp the programmed charge current and charge voltage. this feature effectively avoids damage to the battery if the charger was pro- grammed with invalid data. based on the presence or absence of the ac adapter, the MAX1535 automatically selects the appropriate source for supplying power to the system. a p-channel load switch controlled from the pdl output and a similar p-channel source switch controlled from the pds output are used to implement this function. the MAX1535 can be programmed by a microcontroller (c) to perform a relearning, or conditioning, cycle in which the battery is isolated from the charger and completely discharged through the system load. when the battery reaches 100% depth of discharge, it is recharged to full capacity (contact the battery-pack manufacturers for the 100% depth of discharge threshold). the circuit shown in figure 1 demonstrates a typical application for smart-battery systems. setting charge voltage the smbus specification allows for a 16-bit chargevoltage() command that translates to a 1mv lsb and a 65.535v full-scale voltage; therefore, the chargevoltage() code corresponds to the output volt- age in millivolts. the MAX1535 ignores the first 4 lsbs, and uses the next 11 bits to control the voltage dac. the charge voltage range of the MAX1535 is 0 to 19.200v. all codes requesting charge voltage greater than 19.200v result in a voltage setting of 19.200v. all codes requesting charge voltage below 1.024v result in a voltage set point of zero, which terminates charging. the vmax pin can be used to set an upper limit to the charge voltage. this feature supercedes the value set with the chargevoltage() command when charge volt- age is greater than v charge _ max . the voltage range of vmax is from 0 to v ref . the maximum charge volt- age can be related to the voltage on vmax using the following equation: where v vmax is the voltage on the vmax pin. setting charge current the smbus specification allows for a 16-bit chargecurrent() command that translates to a 1ma lsb and a 65.535a full-scale current using a 10m ? current-sense resistor (r2 in figure 1). equivalently, the chargecurrent() value sets the voltage across csip and csin inputs in 10v per lsb increment. the MAX1535 ignores the first 7 lsbs and uses the next 6 bits to control the current dac. the charge-current range of the MAX1535 is 0 to 8.064a using a 10m ? current-sense resistor. all codes requesting charge current above 8.064a result in a current setting of 8.064a. all codes requesting charge current between 1ma to 128ma result in a current setting of 128ma. the default charge-current setting at power-on reset (por) is also 128ma. the imax pin can be used to set an upper limit to the charge current. this feature supercedes the value set with the chargecurrent() command when charge cur- rent is greater than i charge _ max . the voltage range of imax is from 0 to v ref . the maximum charge current can be related to the voltage on imax using the follow- ing equation: where v imax is the voltage on the imax pin. i a v v charge max imax _ = 5 v v v v charge max vmax _ = 5
MAX1535 highly integrated level 2 smbus battery charger 14 ______________________________________________________________________________________ cssp cssn ldo dhi dlov dlo pgnd csip csin batt gnd dcin acin ccs acok v dd ccv cci dac ref input v dd scl sda temp gnd host batt+ scl sda temp batt- smart battery ac adapter input 8.5v to 24v r3 365k ? 1% r4 49.9k ? 1% c6 1 f d1 p3 r1 0.01 ? r6 20k ? l1 4.3 h n1 p1 gnd pgnd r2 0.01 ? r5 1m ? gpio v cc src pds c11 0.1 f c7 1 f c8 1 f r11 33 ? vmax imax c12 0.01 f c13 0.01 f c14 0.01 f c10 0.1 f c1 22 f c2 22 f p4 (optional) int r7 10k ? r8 10k ? r9 10k ? r10 10k ? pdl p2 r12 14.7k ? 1% r13 100k ? 1% r14 137k ? 1% r15 49.9k ? 1% to system load c5 1 f scl sda thm dhiv c3 22 f c4 22 f c9 1 f MAX1535 figure 1. standard application circuit
MAX1535 highly integrated level 2 smbus battery charger ______________________________________________________________________________________ 15 setting input-current limit the total input current, from a wall cube or other dc source, is the sum of the system supply current and the current required by the charger. the MAX1535 reduces the source current by decreasing the maximum charge current when the input current exceeds the set input current limit. this technique does not truly limit the input current. as the system supply current rises, the available charge current drops proportionally to zero. thereafter, the total input current can increase without limit. an internal amplifier compares the differential voltage between cssp and cssn to a scaled voltage set by the inputcurrent() command over the smbus. the total input current is the sum of the device supply current, the charger input current, and the system load current. the device supply current is minimal (6ma, max) in comparison to the charger current and system load. the total input current can be estimated as follows: where is the efficiency of the dc-to-dc converter (typically 85% to 95%). the MAX1535 allows for a 16-bit inputcurrent() com- mand that translates to a 1ma lsb and a 65.535a full- scale current using a 10m ? current-sense resistor (r1 in figure 1). equivalently, the inputcurrent() value sets the voltage across cssp and cssn inputs in 10v per lsb increments. the MAX1535 ignores the first 7 lsbs and uses the next 6 bits to control the input-current dac. the input-current range of the MAX1535 is from 256ma to 11.004a. all codes requesting input current above 11.004a result in an input-current setting of 11.004a. all codes requesting input current between 1ma to 256ma result in an input-current setting of 256ma. the default input-current-limit setting at por is 256ma. when choosing the current-sense resistor r1, carefully calculate its power rating. take into account variations in the system s load current and the overall accuracy of the sense amplifier. note that the voltage drop across r1 contributes additional power loss, which reduces efficiency. system currents normally fluctuate as portions of the system are powered up or put to sleep. without input- current regulation, the input source must be able to deliver the maximum system current and the maximum charger-input current. by using the input-current-limit circuit, the output-current capability of the ac wall adapter can be lowered, reducing system cost. ldo regulator an integrated low dropout (ldo) linear regulator pro- vides a 5.4v supply derived from dcin, which can deliver at least 10ma of load current. the ldo powers the gate driver of the low-side n-channel mosfet in the dc-to-dc converter. see the mosfet drivers sec- tion. the ldo also biases the 4.096v reference and most of the control circuitry. bypass ldo to gnd with a 1f ceramic capacitor. v dd supply the v dd input provides power to the smbus interface and the thermistor comparators. connect v dd to ldo, or apply an external supply to v dd to keep the smbus interface active while the supply to dcin is removed. operating conditions table 1 is a summary of the following four MAX1535 operating states: ac present. when dcin is greater than 7.5v, the ac adapter is considered to be present. in this condi- tion, both the ldo and ref function properly and battery charging is allowed. the ac_present bit (bit 15) in the chargerstatus() register is set to 1. power fail. when dcin is less than batt + 0.3v, the part is in the power-fail state since the charger does ii i vv input load charge batt in =+ () () [] / operating states input conditions ac present power fail battery batt undervoltage v dd undervoltage dcin v dcin > 7.5v v dcin < v batt + 0.3v xx x thm xxv thm < 0.91 v dd xx batt x v batt > v dcin - 0.3v xv batt < 2.5v x v dd xx x x v dd < 2.5v table 1. summary of operating states x = don? care.
MAX1535 highly integrated level 2 smbus battery charger 16 ______________________________________________________________________________________ linear regulator reference logic and dead time dc-to-dc converter lvc level shifter level shifter daci dacs dacv smbus csip csin cssp cssn vmax imax batt ccv cci ccs v dd scl sda pds pdl dcin ldo ref acin acok src dhi dhiv dlov dlo pgnd ref/2 batt dcin dh dl csi lvc reset dcin batt gnd src src-10v src 1m ? 100k ? MAX1535 int gmv gmi gms figure 2. system functional diagram
MAX1535 highly integrated level 2 smbus battery charger ______________________________________________________________________________________ 17 not have enough input voltage to charge the battery. in power fail, pds turns off the input p-channel mosfet switch and the power_fail bit (bit 13) in the chargerstatus() register is set to 1. battery present. when thm is less than 91% of v dd , the battery is considered to be present. the MAX1535 uses the thm pin to detect whether a bat- tery is connected to the charger. when the battery is present, the battery_present bit (bit 14) in the chargerstatus() register is set to 1. battery undervoltage. when batt is less than 2.5v, the battery is considered to be in an undervoltage state. this condition causes the charger to reduce its current compliance to 128ma. the content of the chargecurrent() register is unaffected. when the batt voltage exceeds 2.7v, normal charging resumes. chargevoltage() is unaffected and can be set as low as 1.024v. v dd undervoltage. when v dd is less than 2.5v, the v dd supply is considered to be in an undervoltage state. the smbus interface does not respond to commands. coming out of the undervoltage condi- tion, the part is in its por state. no charging occurs when v dd is in the undervoltage state. smbus interface the MAX1535 receives control inputs from the smbus interface. the serial interface complies with the smbus protocols as documented in system management bus specification v1.1 and can be downloaded from www.sbs-forum.org. the charger functionality complies with intel/duracell smart charger specifications for a level 2 charger, as well as supporting input current limit and power source selection functions. the MAX1535 uses the smbus read-word and write- word protocols (figure 3) to communicate with the bat- figure 3. smbus a) write-word and b) read-word protocols preset to 0b0001001 d7 d0 d15 d8 chargermode() = 0x12 chargecurrent() = 0x14 chargevoltage() = 0x15 alarmwarning() = 0x16 inputcurrent() = 0x3f preset to 0b0001001 preset to 0b0001001 d7 d0 d15 d8 chargerspecinfo() = 0x11 chargerstatus() = 0x13 0 1b ack 0 msb lsb 1b 8 bits ack command byte 0 msb lsb 1b 7 bits w slave address s 0 msb lsb 1b 8 bits ack low data byte p 0 msb lsb 1b 8 bits ack high data byte a) write-word format b) read-word format legend: s = start condition or repeated start condition p = stop condition ack = acknowledge (logic low) nack = not acknowledge (logic high) w = write bit (logic low) r = read bit (logic high) master to slave slave to master high data byte nack 8 bits 1b msb lsb 1 p low data byte ack 8 bits 1b msb lsb 0 slave address r 7 bits 1b msb lsb 1 ack 1b 0 command byte ack 8 bits 1b msb lsb 0 s ack 1b 0 s slave address w 7 bits 1b msb lsb 0
MAX1535 highly integrated level 2 smbus battery charger 18 ______________________________________________________________________________________ tery being charged, as well as with any host system that monitors the battery-to-charger communications as a level 2 smbus charger. the MAX1535 is an smbus slave device and does not initiate communication on the bus. it responds to the 7-bit address 0b0001001. in addition, the MAX1535 has two identification (id) regis- ters: a 16-bit device id register (0x0006), and a 16-bit manufacturer id register (0x004d). the data input sda and clock input scl pins have schmitt-trigger inputs that can accommodate slow edges; however, the rising and falling edges should still be faster than 1s and 300ns, respectively. communication starts with the master signaling the beginning of a transmission with a start condition, which is a high-to-low transition on sda, while scl is high. when the master has finished communicating with the slave, the master issues a stop condition, which is a low-to-high transition on sda, while scl is high. the bus is then free for another transmission. figures 4 and 5 show the timing diagram for signals on the smbus interface. the address byte, command byte, and data byte are transmitted between the start and stop conditions. the sda state is allowed to change only while scl is low, except for the start smbclk ab cd e fg h i j k smbdata t su:sta t hd:sta t low t high t su:dat t hd:dat t hd:dat t su:sto t buf a = start condition b = msb of address clocked into slave c = lsb of address clocked into slave d = r/w bit clocked into slave e = slave pulls smbdata line low l m f = acknowledge bit clocked into master g = msb of data clocked into slave h = lsb of data clocked into slave i = slave pulls smbdata line low j = acknowledge clocked into master k = acknowledge clock pulse l = stop condition, data executed by slave m = new start condition figure 4. smbus write timing smbclk a = start condition b = msb of address clocked into slave c = lsb of address clocked into slave d = r/w bit clocked into slave ab cd e fg h i j smbdata t su:sta t hd:sta t low t high t su:dat t hd:dat t su:dat t su:sto t buf k e = slave pulls smbdata line low f = acknowledge bit clocked into master g = msb of data clocked into master h = lsb of data clocked into master i = acknowledge clock pulse j = stop condition k = new start condition figure 5. smbus read timing
MAX1535 highly integrated level 2 smbus battery charger ______________________________________________________________________________________ 19 and stop conditions. data is transmitted in 8-bit bytes and is sampled on the rising edge of scl. nine clock cycles are required to transfer each byte in or out of the MAX1535 since either the master or the slave acknowl- edges the receipt of the correct byte during the ninth clock. the MAX1535 supports the charger commands as described in tables 2 9. battery-charger commands the MAX1535 supports seven battery charger com- mands that use either write-word or read-word proto- cols, as summarized in table 2. chargerspec() the chargerspec() command uses the read-word pro- tocol (figure 3). the command code for chargerspec() is 0x11(0b00010001). table 3 lists the functions of the data bits (d0 d15). bit 0 refers to the d0 bit in the read-word protocol. the MAX1535 complies with level 2 smart- battery charger specification revision 1.1; therefore, the chargerspec() command returns 0x0002. chargermode() the chargermode() command uses the write-word protocol (figure 3). the command code for chargermode() is 0x12 (0b00010010). table 4 lists the functions of the data bits (d0 d15). bit 0 refers to the d0 bit in the write-word protocol. to charge a battery that has a thermistor impedance in the hot range (i.e., thermistor_hot = 1 and thermistor_ur = 0), the host must use the chargermode() command to clear hot_stop after the battery is inserted. the hot_stop bit returns to its default power-up condition (1) whenever the battery is removed. chargerstatus() the chargerstatus() command uses the read-word protocol (figure 3). the command code for chargerstatus() is 0x13 (0b00010011). table 5 describes the functions of the data bits (d0 d15). bit 0 refers to the d0 bit in the read-word protocol. the chargerstatus() command returns information about thermistor impedance and the MAX1535 s inter- nal state. the latched bits, thermistor_hot and alarm_inhibited, are cleared whenever battery_present = 0 or chargermode() is written with por_reset = 1. the alarm_inhibited status bit can also be cleared by writing a new charge current or charge voltage. chargecurrent() (por: 0x0080) the chargecurrent() command uses the write-word protocol (figure 3). the command code for chargecurrent() is 0x14 (0b00010100). the 16-bit binary number formed by d15 d0 represents the charge-current set point in milliamps. however, the res- olution of the MAX1535 is 128ma in setting the charge current; bits d0 d6 are ignored as shown in table 6. the d13, d14, and d15 bits are also ignored. figure 6 shows the mapping between the charge-current set point and the chargecurrent() code. all codes request- ing charge current above 8.064a result in a current overrange, limiting the charging current to 8.064a. all codes requesting charge current between 1ma to 128ma result in a current setting of 128ma. a 10m ? current-sense resistor (r2 in figure 1) is required to achieve the correct code/current scaling. command command name read/write description por state status bits affected 0x11 chargerspec() read only charger specification 0x0002 n/a 0x12 chargermode() write only charger mode n/a charge_inhibited, alarm_inhibited, thermistor_hot 0x13 chargerstatus() read only charger status n/a n/a 0x14 chargecurrent() write only charge-current setting 0x0080 current_not_reg, current_or 0x15 chargevoltage() write only charge-voltage setting 0x4b00 voltage_not_reg, voltage_or 0x16 alarmwarning() write only alarm warning n/a n/a 0x3f inputcurrent() write only input current-limit setting 0x0080 current_not_reg 0xfe deviceid() read only device id 0x0006 n/a 0xff manufacturerid() read only manufacturer id 0x004d n/a table 2. battery-charger command summary
MAX1535 highly integrated level 2 smbus battery charger 20 ______________________________________________________________________________________ the default charge-current setting at por is 128ma. thus, the first time a MAX1535 powers up, the charge current is regulated at 128ma. anytime the battery is removed, the chargecurrent() register returns to its por state. chargevoltage() (por: 0x4b00) the chargevoltage() command uses the write-word protocol (figure 3). the command code for chargevoltage() is 0x15 (0b00010101). the 16-bit binary number formed by d15 d0 represents the charge-voltage set point in millivolts. however, the res- olution of the MAX1535 is 16mv in setting the charge voltage; the d0 d3 bits are ignored as shown in table 7. the d15 bit is also ignored. figure 7 shows the map- ping between the charge-voltage set point and the chargevoltage() code. all codes requesting charge voltage greater than 19.200v result in a voltage over- range, limiting the charge voltage to 19.200v. all codes requesting charge voltage below 1024mv result in a voltage set point of zero, which terminates charging. the default charge-voltage setting at por is 19.200v. thus, the first time a MAX1535 powers up, the charge voltage is regulated at 19.200v. anytime the battery is removed, the chargevoltage() register returns to its por state. alarmwarning() the alarmwarning() command uses the write-word pro- tocol (figure 3). the command code for alarmwarning() is 0x16 (0b00010110). alarmwarning() sets the alarm_inhibited status bit in the MAX1535 if d15, d14, d13, d12, or d11 of the write-word protocol equals 1. table 8 summarizes the alarmwarning() command s function. the alarm_inhibited status bit remains set until the battery is removed, a chargermode() command is written with the por_reset bit set, or new chargecurrent() and chargevoltage() values are written. as long as alarm_inhibited = 1, the MAX1535 switching regulator remains off. inputcurrent() (por: 0x0080) the inputcurrent() command uses the write-word pro- tocol (figure 3). the command code for inputcurrent() is 0x3f (0b00111111). the 16-bit binary number formed by d15 d0 represents the charge-current set point in milliamps. however, the resolution of the MAX1535 is 256ma in setting the charge current; the d0 d6 bits are ignored as shown in table 9. the d13, d14, and d15 bits are also ignored. figure 8 shows the mapping between the input-current set point and the inputcurrent() code. all codes requesting input current greater than 11.004a result in an input-current over- range, limiting the input current to 11.004a. all codes requesting input current between 1ma and 256ma bit bit name description 0 charger_spec returns a zero for version 1.1 1 charger_spec returns a 1 for version 1.1 2 charger_spec returns a zero for version 1.1 3 charger_spec returns a zero for version 1.1 4 selector_support returns a zero, indicating no smart-battery selector functionality 5 reserved returns a zero 6 reserved returns a zero 7 reserved returns a zero 8 reserved returns a zero 9 reserved returns a zero 10 reserved returns a zero 11 reserved returns a zero 12 reserved returns a zero 13 reserved returns a zero 14 reserved returns a zero 15 reserved returns a zero table 3. chargerspec() command: 0x11
MAX1535 highly integrated level 2 smbus battery charger ______________________________________________________________________________________ 21 result in a current setting of 256ma. a 10m ? current- sense resistor (r1 in figure 1) is required to achieve the correct code/current scaling. the default input current-limit setting at por is 256ma. thus, the first time a MAX1535 powers up, the input current is limited to 256ma. anytime the battery is removed, the inputcurrent() register returns to its por state. interrupts and alert response address the MAX1535 requests an interrupt by pulling the int pin low. an interrupt is normally requested when there is a change in the state of the chargerstatus() bits power_fail (bit 13), battery_present (bit 14), or ac_present (bit 15). therefore, the int pin pulls low whenever the ac adapter is connected or disconnected, the battery is inserted or removed, bit bit name description 0 inhibit_charge 0* = allow normal operation; clear the chg_inhibited flip-flop. 1 = turn off the charger; set the chg_inhibited flip-flop. the chg_inhibited flip-flop is not affected by any other commands. 1 enable_polling not implemented 2 por_reset 0* = no change. 1 = change the chargevoltage() to 0x4b00 and the chargecurrent() to 0x0080; clear the thermistor_hot and alarm_inhibited flip-flops. 3 reset_to_zero 0* = no change. 1 = set the chargecurrent() and chargevoltage() to zero even if the inhibited_charge bit is zero. 4 ac_present_mask 0* = interrupt on either edge of the ac_present status bit. 1 = do not interrupt because of an ac_present bit change. 5 battery_present_mask 0* = interrupt on either edge of the battery_present status bit. 1 = do not interrupt because of a battery_present bit change. 6 power_fail_mask 0* = interrupt on either edge of the power_fail status bit. 1 = do not interrupt because of a power_fail bit change. 7 not implemented 8 calibration_enable 0* = when dcin > batt + 100mv, pds pulls low and pdl pulls high. 0 = when dcin < batt + 100mv, pds pulls high and pdl pulls low. 1 = when thm < 91% and dcin > batt + 100mv, pds pulls high and pdl pulls low. 1 = when thm > 91% and dcin > batt + 100mv, pds pulls high and pdl pulls low. 9 not implemented 10 hot_stop 0 = the thermistor_hot status bit does not turn off the charger. 1* = the thermistor_hot status bit does turn off the charger. thermistor_hot is reset by either por_reset or battery_present = 0. 11 not implemented 12 not implemented 13 not implemented 14 not implemented 15 not implemented table 4. chargermode() command: 0x12 * indicates por state.
MAX1535 highly integrated level 2 smbus battery charger 22 ______________________________________________________________________________________ bit bit name description 0 charge_inhibited 0* = ready to charge the smart battery. 1 = charging is inhibited; charge current is 0ma. this status bit returns the value of the chg_inhibited flip-flop. 1 master_mode always returns a zero 2 voltage_not_reg 0 = battery voltage is limited at the set point. 1 = battery voltage is less than the set point. 3 current_not_reg 0 = battery current is limited at the set point. 1 = battery current is less than the set point. 4 level_2 always returns a 1 5 level_3 always returns a zero 6 current_or 0 = the chargecurrent() value is valid for the MAX1535. 1 = the chargecurrent() value exceeds the MAX1535 output range, i.e., programmed chargecurrent() exceeds 0x1f80. 7 voltage_or 0 = the chargevoltage() value is valid for the MAX1535. 1 = the chargevoltage() value exceeds the MAX1535 output range, i.e., programmed chargevoltage() exceeds 0x4b00. 8 thermistor_or 0 = thm is < 91% of the reference voltage. 1 = thm is > 91% of the reference voltage. 9 thermistor_cold 0 = thm is < 75% of the reference voltage. 1 = thm is > 75% of the reference voltage. 10 thermistor_hot 0 = thm has not dropped to < 23% of the reference voltage. 1 = thm has dropped to < 23% of the reference voltage. thermistor_hot flip-flop cleared by battery_present = 0 or writing a 1 into the por_reset bit in the chargermode() command. 11 thermistor_ur 0 = thm is > 5% of the reference voltage. 1 = thm is < 5% of the reference voltage. 12 alarm_inhibited returns the state of the alarm_inhibited flip-flop. this flip-flop is set by either a watchdog timeout or by writing an alarmwarning() command with bits 12, 14, or 15 set. this flip-flop is cleared by battery_present = 0, or writing a 1 into the por_reset bit in the chargermode() command, or by receiving successive chargevoltage() and chargecurrent() commands. 13 power_fail 0 = acin is above the ref/2 threshold. 1 = acin is below the ref/2 threshold. 14 battery_present 0 = no battery is present (v thm > 0.91 v dd ). 1 = battery is present (v thm < 0.91 v dd ). 15 ac_present 0 = dcin is below the 7.5v undervoltage threshold. 1 = dcin is above the 7.5v undervoltage threshold. table 5. chargerstatus() command: 0x13 * indicates por state.
MAX1535 highly integrated level 2 smbus battery charger ______________________________________________________________________________________ 23 or the charger goes in or out of dropout. the interrupts from each of the chargerstatus() bits can be masked by an associated chargermode() bit power_fail_mask (bit 6), battery_present_mask (bit 5), or ac_present_mask (bit 4). interrupts are cleared by sending a command to the alertresponse() address, 0x19, using a modified receive-byte protocol. in this protocol, the devices that set an interrupt try to respond by transmitting their addresses, and the devices with the highest priority or most leading zeros are recognized and cleared. this process is repeated until all devices requesting inter- rupts are addressed and cleared. the MAX1535 responds to the alertresponse() address with 0x13, which is its address and a trailing 1. bit bit name description 0 not used. normally a 1ma weight. 1 not used. normally a 2ma weight. 2 not used. normally a 4ma weight. 3 not used. normally an 8ma weight. 4 not used. normally a 16ma weight. 5 not used. normally a 32ma weight. 6 not used. normally a 64ma weight. 7 charge current, daci 0 0 = adds 0ma of charger-current compliance. 1 = adds 128ma of charger-current compliance. 8 charge current, daci 1 0 = adds 0ma of charger-current compliance. 1 = adds 256ma of charger-current compliance. 9 charge current, daci 2 0 = adds 0ma of charger-current compliance. 1 = adds 512ma of charger-current compliance. 10 charge current, daci 3 0 = adds 0ma of charger-current compliance. 1 = adds 1024ma of charger-current compliance. 11 charge current, daci 4 0 = adds 0ma of charger-current compliance. 1 = adds 2048ma of charger-current compliance, 8064ma max. 12 charge current, daci 5 0 = adds 0ma of charger-current compliance. 1 = adds 4096ma of charger-current compliance, 8064ma max. 13 not used. normally an 8192ma weight. 14 not used. normally a 16384ma weight. 15 not used. normally a 32768ma weight. table 6. chargecurrent() command: 0x14 128 2048 4096 8064 0xffff 0x0080 0x0800 0x1000 0x1f80 chargecurrent() code charge-current set point (ma) figure 6. chargecurrent() code to charge-current set point mapping (r 2 = 10m ? )
MAX1535 highly integrated level 2 smbus battery charger 24 ______________________________________________________________________________________ charger timeout the MAX1535 includes a timer that terminates charging if the charger has not received a chargevoltage() or chargecurrent() command in 175s. during charging, the timer is reset each time a chargevoltage() or chargecurrent() command is received; this ensures that the charging cycle is not terminated. thermistor comparators four thermistor comparators evaluate the voltage at the thm input to determine the battery temperature. this input is meant to be used with the internal thermistor connected to ground inside the battery pack. connect the output of the battery thermistor to thm. connect a pullup resistor from thm to v dd . the resistive voltage- divider sets the voltage at thm. bit bit name description 0 not used. normally a 1mv weight. 1 not used. normally a 2mv weight. 2 not used. normally a 4mv weight. 3 not used. normally an 8mv weight. 4 charge voltage, dacv 0 0 = adds 0mv of charge-voltage compliance, 1024mv min. 1 = adds 16mv of charge-voltage compliance. 5 charge voltage, dacv 1 0 = adds 0mv of charge-voltage compliance, 1024mv min. 1 = adds 32mv of charge-voltage compliance. 6 charge voltage, dacv 2 0 = adds 0mv of charge-voltage compliance, 1024mv min. 1 = adds 64mv of charge-voltage compliance. 7 charge voltage, dacv 3 0 = adds 0mv of charge-voltage compliance, 1024mv min. 1 = adds 128mv of charge-voltage compliance. 8 charge voltage, dacv 4 0 = adds 0mv of charge-voltage compliance, 1024mv min. 1 = adds 256mv of charge-voltage compliance. 9 charge voltage, dacv 5 0 = adds 0mv of charge-voltage compliance, 1024mv min. 1 = adds 512mv of charge-voltage compliance. 10 charge voltage, dacv 6 0 = adds 0mv of charge-voltage compliance. 1 = adds 1024mv of charge-voltage compliance. 11 charge voltage, dacv 7 0 = adds 0mv of charge-voltage compliance. 1 = adds 2048mv of charge-voltage compliance. 12 charge voltage, dacv 8 0 = adds 0mv of charge-voltage compliance. 1 = adds 4096mv of charge-voltage compliance. 13 charge voltage, dacv 9 0 = adds 0mv of charge-voltage compliance. 1 = adds 8192mv of charge-voltage compliance. 14 charge voltage, dacv 10 0 = adds 0mv of charge-voltage compliance. 1 = adds 16384mv of charge-voltage compliance, 19200mv max. 15 not used. normally a 32768mv weight. table 7. chargevoltage() command: 0x15 1024 4200 8400 19200 16800 0xffff 0x0400 0x1060 0x20d0 0x4b00 0x41a0 chargevoltage() code charge-voltage set point (mv) figure 7. chargevoltage() code to charge-voltage set point mapping
MAX1535 highly integrated level 2 smbus battery charger ______________________________________________________________________________________ 25 thermistor bits table 10 summarizes the conditions for setting the ther- mistor bits and how these 4 bits affect the charging sta- tus when a 10k ? pullup resistor is connected between v dd and thm: thermistor_or bit is set when the thermistor value is greater than 100k ? . this indicates that the thermistor is open or a battery is not present. the charger is set to por, and the battery_present bit is cleared. thermistor_cold bit is set when the thermistor value is greater than 30k ? . the thermistor indicates a cold battery. this bit does not affect charging. thermistor_hot bit is set when the thermistor value is less than 3k ? . this is a latched bit and is cleared by removing the battery or sending a por with the chargermode() command. the charger is ter- minated unless the hot_stop bit is cleared in the chargermode() command or the thermistor_ur bit is set. see tables 4 and 10. thermistor_ur bit is set when the thermistor value is less than 500 ? (i.e., thm is grounded). bit bit name description 0 error code not used 1 error code not used 2 error code not used 3 error code not used 4 fully_discharged not used 5 fully_charged not used 6 discharging not used 7 initializing not used 8 remaining_time_alarm not used 9 remaining_capacity_alarm not used 10 reserved not used 11 terminate_discharge_alarm not used 12 over_temp_alarm 0 = charge normally. 1 = terminate charging. 13 other_alarm 0 = charge normally. 1 = terminate charging. 14 terminate_charge_alarm 0 = charge normally. 1 = terminate charging. 15 over_charge_alarm 0 = charge normally. 1 = terminate charging. table 8. alarmwarning() command: 0x16 256 4096 8192 11008 0xffff 0x080 0x0800 0x1000 0x1580 inputcurrent() code input-current set point (ma) figure 8. inputcurrent() code to input current-limit mapping
MAX1535 highly integrated level 2 smbus battery charger 26 ______________________________________________________________________________________ multiple bits may be set depending on the value of the thermistor (e.g., a thermistor that is 450 ? causes both the thermistor_hot and the thermistor_ur bits to be set). the thermistor may be replaced with fixed- value resistors in battery packs that do not require the thermistor as a secondary fail-safe indicator. in that case, it is the responsibility of the battery pack elec- tronics to manipulate the resistance to obtain correct charger behavior. ac adapter detection and power source selection the MAX1535 includes a hysteretic comparator that detects the presence of an ac power adapter. the MAX1535 automatically delivers power to the system load from an appropriate available power source. when the adapter is present, the open-drain acok output becomes low impedance and the p-channel source switch (p1 in figure 1) is turned on by pds, thereby powering the system. the switch threshold at acin is 2.048v. use a resistive voltage-divider from the adapter s output to the acin pin to set the appropriate detection threshold. when charging, the battery is iso- lated from the system load with the p-channel load switch (p2 in figure 1), which is switched off by pdl. when the adapter is absent, the drive to the switches changes state in a fast break-before-make sequence. pdl begins to turn on 7.5s after pds begins to turn off. the threshold for selecting between the pdl and pds switches is set based on the voltage difference between the dcin and the batt pins. if this voltage difference drops below 100mv, the pds is switched off and pdl is switched on. under these conditions, the MAX1535 is completely powered down. the pdl switch is kept on with a 100k ? pulldown resistor when the ac adapter is removed. the drivers for pdl and pds are fully integrated. the positive bias inputs for the drivers connect to the src pin and the negative bias inputs connect to a negative regulator referenced to src. with this arrangement, the drivers can swing from src to approximately 10v below src. dc-to-dc converter the MAX1535 employs a synchronous step-down dc- to-dc converter with a p-channel high-side mosfet switch and an n-channel low-side synchronous rectifi- er. the MAX1535 features a pseudofixed-frequency, current-mode control scheme with cycle-by-cycle cur- rent limit. the off-time is dependent upon v dcin , v batt , and a time constant, with a minimum t off of 300ns. the MAX1535 can also operate in discontinuous conduction mode for improved light-load efficiency. the operation of the dc-to-dc controller is determined by the following four comparators as shown in the func- tional diagram in figure 9: imin. compares the control signal (lvc) against 100mv (typ). when lvc voltage is less than 100mv, the comparator output is low and a new cycle can- not start. ccmp. compares lvc against the charge-current feedback signal (csi). the comparator output is high and the high-side mosfet on-time is terminat- ed when the csi voltage is higher than lvc. imax. compares csi to 2v (corresponding to 10a when r2 = 10m ? ). the comparator output is high and the high-side mosfet on-time is terminated when csi voltage is higher than the threshold. a new cycle cannot start until the imax comparator output goes low. zcmp. compares csi to 100mv (corresponding to 500ma when r2 = 10m ? ). the comparator output is high and both mosfets are turned off when csi voltage is lower than the threshold. ccv, cci, ccs, and lvc control blocks the MAX1535 controls input current (ccs control loop), charge current (cci control loop), or charge voltage (ccv control loop), depending on the operating condi- tion. the three control loops, ccv, cci, and ccs, are brought together internally at the lowest voltage clamp (lvc) amplifier. the output of the lvc amplifier is the feedback control signal for the dc-to-dc controller. the minimum voltage at ccv, cci, or ccs appears at the output of the lvc amplifier and clamps the other two control loops to within 0.3v above the control point. clamping the other two control loops close to the low- est control loop ensures fast transition with minimal overshoot when switching between different control loops (see the compensation section). continuous-conduction mode with sufficient charge current, the MAX1535 inductor current never reaches zero, which is defined as contin- uous-conduction mode. the regulator switches at 400khz (nominal) if it is not in dropout (v batt < 0.88 v dcin ). the controller starts a new cycle by turning on the high-side p-channel mosfet and turning off the low-side n-channel mosfet. when the charge-current feedback signal (csi) is greater than the control point (lvc), the ccmp comparator output goes high and the controller initiates the off-time by turning off the high- side p-channel mosfet and turning on the low-side n- channel mosfet. the operating frequency is governed
MAX1535 highly integrated level 2 smbus battery charger ______________________________________________________________________________________ 27 thermistor status bit description conditions wake-up charge controlled charge thermistor_or overrange r thm > 100k ? or v thm > 0.91 v dd not allowed not allowed thermistor_cold cold r thm > 30k ? or v thm > 0.75 v dd allowed for timeout period allowed (none) normal 3k ? < r thm < 30k ? or 0.23 v dd < v thm < 0.75 v dd allowed for timeout period allowed thermistor_hot hot r thm < 3k ? or v thm < 0.23 v dd not allowed not allowed thermistor_ur underrange r thm < 500 ? or v thm < 0.05 v dd allowed allowed table 10. thermistor bit settings bit bit name description 0 not used. normally a 2ma weight. 1 not used. normally a 4ma weight. 2 not used. normally an 8ma weight. 3 not used. normally a 16ma weight. 4 not used. normally a 32ma weight. 5 not used. normally a 64ma weight. 6 not used. normally a 128ma weight. 7 input current, dacs 0 0 = adds 0ma of input-current compliance. 1 = adds 256ma of input-current compliance. 8 input current, dacs 1 0 = adds 0ma of input-current compliance. 1 = adds 512ma of input-current compliance. 9 input current, dacs 2 0 = adds 0ma of input-current compliance. 1 = adds 1024ma of input-current compliance. 10 input current, dacs 3 0 = adds 0ma of input-current compliance. 1 = adds 2048ma of input-current compliance. 11 input current, dacs 4 0 = adds 0ma of input-current compliance. 1 = adds 4096ma of input-current compliance. 12 input current, dacs 5 0 = adds 0ma of input-current compliance. 1 = adds 8192ma of input-current compliance. 13 not used. normally a 16384ma weight. 14 not used. normally a 32768ma weight. 15 not used. normally a 65536ma weight. table 9. inputcurrent() command: 0x3f
MAX1535 highly integrated level 2 smbus battery charger 28 ______________________________________________________________________________________ by the off-time and is dependent upon v dcin and v batt . the off-time is set by the following equation: the on-time can be determined using the following equation: the switching frequency can then be calculated: these equations describe the controller s pseudofixed- frequency performance over the most common operat- ing conditions. at the end of the fixed off-time, the controller initiates a new cycle if the control point (lvc) is greater than 100mv (imin comparator output is high), and the peak charge current is less than the cycle-by-cycle limit (imax comparator output is low). if the peak charge cur- rent exceeds the imax comparator threshold, the on-time is terminated. the imax comparator governs the maxi- mum cycle-by-cycle current limit and is internally set to 10a (when r2 = 10m ? ). the cycle-by-cycle current limit effectively protects against sudden overcurrent faults. if during the off-time the inductor current goes to zero, the zcmp comparator output pulls high, turning off the low-side mosfet. both the high- and low-side mosfets are turned off until another cycle is ready to begin. the MAX1535 enters into the discontinuous conduction mode (see the discontinuous conduction section). there is a 0.3s minimum off-time when the (v dcin - v batt ) differential becomes too small. if v batt 0.88 x v dcin , then the threshold for minimum off-time is reached and the off-time is fixed at 0.3s. the switch- ing frequency in this mode varies according to the equation: discontinuous conduction the MAX1535 enters discontinuous-conduction mode when the output of the lvc control point falls below 100mv. for r2 = 10m ? , this corresponds to 0.5a: in discontinuous mode, a new cycle is not started until the lvc voltage rises above 100mv. discontinuous mode operation can occur during conditioning charge of overdischarged battery packs, when the charge cur- rent has been reduced sufficiently by the ccs control loop, or when the charger is in constant-voltage mode with a nearly full battery pack. compensation the charge voltage, charge current, and input current- limit regulation loops are compensated separately and independently at the ccv, cci, and ccs pins. ccv loop compensation the simplified schematic in figure 10 is sufficient to describe the operation of the MAX1535 when the voltage loop (ccv) is in control. the required compensation net- work is a pole-zero pair formed with c cv and r cv . the pole is necessary to roll off the voltage loop s response at low frequency. the zero is necessary to compensate the pole formed by the output capacitor and the load. r esr is the equivalent series resistance (esr) of the charger out- put capacitor (c out ). r l is the equivalent charger output load, where r l = ? v batt / ? i chg . the equivalent output impedance of the gmv amplifier, r ogmv , is greater than 10m ? . the voltage amplifier transconductance, gmv = 0.125a/mv. the dc-to-dc converter transconductance is dependent upon the charge current-sense resistor r2: where a csi = 20, and r2 = 0.01 ? in the typical appli- cation circuits, so gm out = 3.33a/v. the loop transfer function (ltf) is given by: the poles and zeros of the voltage-loop transfer function are listed from lowest to highest frequency in table 11. near crossover c cv is much lower impedance than r ogmv . since c cv is in parallel with r ogmv, c cv domi- nates the parallel impedance near crossover. ltf gm r gmv r sc r sc r sc r sc r out l ogmv out esr cv cv cv ogmv out l = + + + + ()() ()() 11 11 gm ar out csi = 1 2 i v r a ch e current for r m min = == 01 20 2 2 05 2 10 . . arg ? f li v s ripple cssn = + 1 03 ( . -v ) batt f tt sw on off = + 1 where i vt l ripple batt off = . t li vv on ripple cssn batt = - ts vv v off dcin batt dcin = ? 25 .
MAX1535 highly integrated level 2 smbus battery charger ______________________________________________________________________________________ 29 additionally, r cv is much higher impedance than c cv and dominates the series combination of r cv and c cv , so: c out is also much lower impedance than r l near crossover so the parallel impedance is mostly capaci- tive and: if r esr is small enough, its associated output zero has a negligible effect near crossover and the loop-transfer function can be simplified as follows: setting the ltf = 1 to solve for the unity-gain frequency yields: for stability, choose a crossover frequency lower than 1/10th of the switching frequency. for example, choose a crossover frequency of 30khz and solving for r cv using the component values listed in figure 1 yields r cv = 20k ? : v batt = 16.8v gmv = 0.125a/mv i chg = 4a gm out = 3.33a/v c out = 2 22f f osc = 400khz r l = 0.2 ? f co_cv = 30khz to ensure that the compensation zero adequately can- cels the output pole, select f z_cv f p_out : c cv (r l /r cv ) c out c cv 4nf (assuming 4 cells and 4a maximum charge current) figure 11 shows the bode plot of the voltage-loop fre- quency response using the values calculated above. r cf gmv gm k cv out co cv out = = 2 10 _ ? f gm gmv r c co cv out cv out _ = 2 ltf gm r sc gmv out cv out = r sc r sc l out l out () 1 1 + ? rscr sc r r ogmv cv cv cv ogmv cv + + ? () () 1 1 imax ccmp imin zcmp csi 2v 100mv 50mv dcin batt lvc r r q q off-time one-shot off-time compute to dh driver to dl driver figure 9. dc-to-dc converter block diagram c cv c out r cv r l r esr r ogmv ccv batt gmv ref gm out figure 10. ccv loop diagram
MAX1535 highly integrated level 2 smbus battery charger 30 ______________________________________________________________________________________ cci loop compensation the simplified schematic in figure 12 is sufficient to describe the operation of the MAX1535 when the bat- tery current loop (cci) is in control. since the output capacitor s impedance has little effect on the response of the current loop, only a simple single pole is required to compensate this loop. a csi is the internal gain of the current-sense amplifier. r2 is the charge current-sense resistor, r2 = 10m ? . r ogmi is the equivalent output impedance of the gmi amplifier, which is greater than 10m ? . gmi is the charge-current amplifier transcon- ductance = 1a/mv. gm out is the dc-to-dc converter transconductance = 3.3a/v. the loop-transfer function is given by: ltf gm a rs gmi r sr c out csi ogmi ogmi ci = + 2 1 name equation description ccv pole lowest frequency pole created by c cv and gmv s finite output resistance. since r ogmv is very large and not well controlled, the exact value for the pole frequency is also not well controlled (r ogmv > 10m ? ). ccv zero voltage-loop compensation zero. if this zero is at the same frequency or lower than the output pole f p_out , then the loop-transfer function approximates a single-pole response near the crossover frequency. choose c cv to place this zero at least one decade below crossover to ensure adequate phase margin. output pole output pole formed with the effective load resistance r l and the output capacitance c out . r l influences the dc gain but does not affect the stability of the system or the crossover frequency. output zero output esr zero. this zero can keep the loop from crossing unity gain if f z_out is less than the desired crossover frequency; therefore, choose a capacitor with an esr zero greater than the crossover frequency. table 11. ccv loop poles and zeros f rc pcv ogmv cv _ = 1 2 f rc zcv cv cv _ = 1 2 f rc p out l out _ = 1 2 f resr c z out out _ = 1 2 frequency (hz) magnitude (db) phase (degrees) 100k 10k 1k 100 10 1 -20 0 20 40 60 80 -40 -90 -45 0 -135 0.1 1m mag phase figure 11. ccv loop response c ci r ogmi cci gmi csi ictl gm out csip rs2 csin figure 12. cci loop diagram
MAX1535 highly integrated level 2 smbus battery charger ______________________________________________________________________________________ 31 this describes a single-pole system. since: the loop-transfer function simplifies to: the crossover frequency is given by: for stability, choose a crossover frequency lower than 1/10th of the switching frequency: c ci = gmi / (2 f co-ci ) choosing a crossover frequency of 30khz and using the component values listed in figure 1 yields c ci > 5.4nf. values for c ci greater than 10 times the minimum value may slow down the current-loop response excessively. figure 13 shows the bode plot of the current-loop fre- quency response using the values calculated above. ccs loop compensation the simplified schematic in figure 14 is sufficient to describe the operation of the MAX1535 when the input current-limit loop (ccs) is in control. since the output capacitor s impedance has little effect on the response of the input current-limit loop, only a single pole is required to compensate this loop. a css is the internal gain of the current-sense amplifier. r1 is the input cur- rent-sense resistor, r1 = 10m ? in the typical application circuits. r ogms is the equivalent output impedance of the gms amplifier, which is greater than 10m ? . gms is the charge-current amplifier transconductance = 1a/mv. gm in is the dc-to-dc converter s input-referred transconductance = (1/d) gm out = (1/d) 3.3a/v. the loop-transfer function is given by: the crossover frequency is given by: for stability, choose a crossover frequency lower than 1/10th of the switching frequency: c cs = 5 gms / (2 f osc ) choosing a crossover frequency of 30khz and using the component values listed in figure 1 yields c cs > 5.4nf. values for ccs greater than 10 times the mini- mum value may slow down the current-loop response excessively. figure 15 shows the bode plot of the input current-limit-loop frequency response using the values calculated above. mosfet drivers the dhi and dlo outputs are optimized for driving moderate-sized power mosfets. the mosfet drive capability is the same for both the low-side and high- side switches. this is consistent with the variable duty factor that occurs in the notebook computer environ- ment where the battery voltage changes over a wide range. an adaptive dead-time circuit monitors the dlo output and prevents the high-side fet from turning on until dlo is fully off. there must be a low-resistance, low-inductance path from the dlo driver to the mos- fet gate for the adaptive dead-time circuit to work properly. otherwise, the sense circuitry in the MAX1535 interprets the mosfet gate as off while there is still charge left on the gate. use very short, wide traces measuring 10 squares to 20 squares or less (1.25mm to 2.5mm wide if the mosfet is 25mm from the device). unlike the dlo output, the dhi output uses a 50ns (typ) delay time to prevent the low-side mosfet from turning on until dhi is fully off. the same layout considerations should be used for routing the dhi sig- nal to the high-side mosfet. since the transition time for a p-channel switch can be much longer than an n-channel switch, the dead time prior to the high-side p-channel mosfet turning on is more pronounced than in other synchronous step-down regulators, which use high-side n-channel switches. on the high-to-low transition, the voltage on the induc- tor s switched terminal flies below ground until the low-side switch turns on. a similar dead-time spike occurs on the opposite low-to-high transition. depending upon the magnitude of the load current, these spikes usually have a minor impact on efficiency. the high-side driver (dhi) swings from src to 5v below src and has a typical impedance of 1 ? sourc- ing and 4 ? sinking. the low-side driver (dlo) swings f gms c co cs cs _ = 2 ltf gms r sr c ogms ogms cs = + 1 since gm ars the loop transfer function sim p lifies to in css = ? 1 1 , : ltf gm a rsi gms r sr c in css ogms ogms cs = + 1 f gmi c co ci ci _ = 2 ltf gmi r sr c ogmi ogmi ci = + 1 gm ars out csi = 1 2
MAX1535 highly integrated level 2 smbus battery charger 32 ______________________________________________________________________________________ from dlov to ground and has a typical impedance of 1 ? sinking and 4 ? sourcing. this helps prevent dlo from being pulled up when the high-side switch turns on due to capacitive coupling from the drain to the gate of the low-side mosfet. this places some restrictions on the mosfets that can be used. using a low-side mosfet with smaller gate-to-drain capacitance can prevent these problems. design procedure table 12 lists the recommended components and refers to the circuit of figure 1. the following sections describe how to select these components. mosfet selection mosfets p2 and p3 (figure 1) provide power to the system load when the ac adapter is inserted. these devices may have modest switching speeds, but must be able to deliver the maximum input current as set by r1. as always, care should be taken not to exceed the device s maximum voltage ratings at the maximum operating temperature. the p-channel/n-channel mosfets (p1, n1) are the switching devices for the step-down regulator. the guidelines for these devices focus on the challenge of obtaining high load-current capability when using high- voltage (>20v) ac adapters. low-current applications usually require less attention. the high-side mosfet (p1) must be able to dissipate the resistive losses plus the switching losses at both v dcin(min) and v dcin(max) . calculate both these sums. ideally, the losses at v dcin(min) should be roughly equal to losses at v dcin(max) , with lower losses in between. if the losses at v dcin(min) are significantly higher than the losses at v dcin(max) , consider increas- ing the size of p1. conversely, if the losses at v dcin(max) are significantly higher than the losses at v in(min) , consider reducing the size of p1. if dcin does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. choose a low-side mosfet that has c cs r ogms gms css cls ccs cssp rs1 cssn gm in system load adapter input figure 14. ccs loop diagram frequency (hz) magnitude (db) 100k 10m 1k 10 -20 0 20 40 60 100 80 -40 -45 0 -90 0.1 mag phase phase (degrees) figure 13. cci loop response frequency (hz) magnitude (db) 100k 10m 1k 10 -20 0 20 40 60 100 80 -40 -45 0 -90 0.1 mag phase phase (degrees) figure 15. ccs loop response
MAX1535 highly integrated level 2 smbus battery charger ______________________________________________________________________________________ 33 the lowest possible on-resistance (r ds(on) ), comes in a moderate-sized package (i.e., one or two 8-pin so, dpak, or d 2 pak), and is reasonably priced. make sure that the dlo gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate-to-drain capacitor caused by the high-side mosfet turning on; otherwise, cross-con- duction problems can occur. since the MAX1535 utilizes p-channel high-side and n- channel low-side mosfets, the switching characteris- tics can be quite different. select devices that have short turn-off times, and make sure that p1(t doff(max) ) - n1(t don(min) ) < 40ns. failure to do so may result in efficiency-killing shoot-through currents. if delay mis- match causes shoot-through currents, consider adding capacitance from gate to source on n1 to slow down its turn-on time. mosfet power dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet, the worst-case power dissipation (pd) due to resistance occurs at the minimum supply voltage: generally, a small high-side mosfet is desired to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power-dissipation limits often limits how small the mos- fet can be. the optimum occurs when the switching (ac) losses equal the conduction (r ds(on) ) losses. high-side switching losses do not usually become an issue until the input is greater than approximately 15v. calculating the power dissipation in p1 due to switch- ing losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn- off times. these factors include the internal gate resis- tance, gate charge, threshold voltage, source inductance, and pc board layout characteristics. the following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including a verification using a thermocouple mounted on p1: where c rss is the reverse transfer capacitance of p1, and i gate is the peak gate-drive source/sink current (4.5a sourcing and 1.1a sinking). switching losses in the high-side mosfet can become an insidious heat problem when maximum ac adapter voltages are applied due to the squared term in the c x v dcin 2 x f sw switching-loss equation. if the high-side mosfet chosen for adequate r ds(on) at low-battery voltages becomes extraordinarily hot when biased from v in(max) , consider choosing another mosfet with lower parasitic capacitance. for the low-side mosfet (n1), the worst-case power dissipation always occurs at maximum input voltage: choose a schottky diode (d1, figure 1) having a for- ward voltage low enough to prevent the n1 mosfet body diode from turning on during the dead time. as a general rule, a diode having a dc current rating equal to 1/3 of the load current is sufficient. this diode is optional and can be removed if efficiency is not critical. inductor selection the charge current, ripple, and operating frequency (off-time) determine the inductor characteristics. inductor l1 must have a saturation current rating of at least the maximum charge current plus 1/2 of the ripple current ( ? il): i sat = i chg + (1/2) ? il the ripple current is determined by: ? il = v batt t off / l if v batt < 0.88v dcin , then: t off = 2.5s (v dcin - v batt ) / v dcin or: t off = 0.3s for v batt > 0.88 v dcin figure 16 illustrates the variation of the ripple current vs. battery voltage when the circuit is charging at 3a with a fixed input voltage of 19v. higher inductor values decrease the ripple current. smaller inductor values require high-saturation current capabilities and degrade efficiency. designs that set lir = ? il / i chg = 0.3 usually result in a good balance between inductor size and efficiency: l vt lir i batt off chg = pd low side v v i r batt dcin load ds on () () -- = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 2 2 pd hs switching vcfi i dcin max rss sw load gate (_ ) () = 2 2 pd high side v v i r batt dcin load ds on () () - = ? ? ? ? ? ? ? ? ? ? ? ? 2 2
MAX1535 highly integrated level 2 smbus battery charger 34 ______________________________________________________________________________________ designation qty description c1 c4 4 22f 20%, 25v x5r ceramic capacitors (2220) tdk c5750x5r1e226m c5, c6 2 1f 10%, 25v x7r ceramic capacitors (1206) murata grm31mr71e105k taiyo yuden tmk316bj105kl tdk c3216x7r1e105k c7, c8, c9 3 1f 10%, 16v x7r ceramic capacitors (0805) murata grm21br71c105k taiyo yuden emk212bj105kg tdk c2012x7r1e105k c10, c11 2 0.1f 10%, 25v x7r ceramic capacitors (0603) murata grm188r71e104k tdk c1608x7r1e104k c12, c13, c14 3 0.01f 10%, 16v x7r ceramic capacitors (0402) murata grp155r71e103k taiyo yuden emk105bj103kv tdk c1005x7r1e103k d1 1 schottky diode, 0.5a, 30v, sod-123 diodes inc. b0530w general semiconductor mbr0530 on semiconductor mbr0530 l1 1 4.3h, 11a, 11.4m ? inductor sumida cep125-4r3mc-u n1 1 mosfet, n-channel, 13.5a, +30v, 8-pin so fairchild fds6670s p1 p4 4 mosfet, p-channel, 13a, -30v, 8-pin so fairchild fds6679z r1, r2 2 10m ? 1%, 1w sense resistor (2512) irc lrc-lrf2512-01-r010-f r3 1 365k ? 1% resistor (0805) r4 1 49.9k ? 1% resistor (0805) r5 1 1m ? 5% resistor (0805) r6 1 20k ? 5% resistor (0603) r7 r10 4 10k ? 5% resistors (0805) r11 1 33 ? 5% resistor (0805) r12, r13 2 1m ? potentiometers (multiturn) bourns 3266w-1-105 or equivalent table 12. recommended components
MAX1535 highly integrated level 2 smbus battery charger ______________________________________________________________________________________ 35 input capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents. nontantalum chemistries (ceramic, aluminum, or os- con) are preferred due to their resilience to power-up surge currents: the input capacitors should be sized so that the tem- perature rise due to ripple current in continuous con- duction does not exceed approximately 10 c. the maximum ripple current occurs at 50% duty factor or v dcin = 2 x v batt , which equates to 0.5 x i chg . if the application of interest does not achieve the maximum value, size the input capacitors according to the worst- case conditions. output capacitor selection the output capacitor absorbs the inductor ripple cur- rent and must tolerate the surge current delivered from the battery when it is initially plugged into the charger. as such, both capacitance and esr are important parameters in specifying the output capacitor as a filter and to ensure the stability of the dc-to-dc converter (see the compensation section.) beyond the stability requirements, it is often sufficient to make sure that the output capacitor s esr is much lower than the battery s esr. either tantalum or ceramic capacitors can be used on the output. ceramic devices are preferable because of their good voltage ratings and resilience to surge currents. applications information smart-battery system background information smart-battery systems have evolved since the concep- tion of the smart-battery system (sbs) specifications. originally, such systems consisted of a smart battery and smart-battery charger that were compatible with the sbs specifications and communicated directly with each other using smbus protocols. modern systems still employ the original commands and protocols, but often use a keyboard controller or similar digital intelli- gence to mediate the communication between the bat- tery and the charger (figure 17). this arrangement permits considerable freedom in the implementation of charging algorithms at the expense of standardization. algorithms can vary from the simple detection of the battery with a fixed set of instructions for charging the battery to highly complex programs that can accommo- date multiple battery configurations and chemistries. microcontroller programs can perform frequent tests on the battery s state of charge and dynamically change the voltage and current applied to enhance safety. multiple batteries can also be utilized with a selector that is programmable over the smbus. batteries that use smbus fuel gauges must sometimes perform a conditioning cycle to calibrate the fuel gauge s reference data for empty and full capacity. this cycle consists of isolating the battery from the charger and discharging it through the system load. when the battery reaches 100% depth of discharge, it is then recharged. the circuit in figure 1 is capable of implementing this feature under software control. to uti- lize the conditioning function, the configuration of the pds switch must be changed to source-connected fets to prevent the ac adapter from supplying current to the system through the mosfet s body diode. the src pin must be connected to the common source node of the back-to-back fets to properly drive the mosfets. it is essential to alert the user that the system is perform- ing a conditioning cycle. if the user terminates the cycle prematurely, the battery may be discharged even though the system was running off an ac adapter for a substantial period of time. if the ac adapter is in fact removed during conditioning, the MAX1535 keeps the pdl switch on and the charger remains off as it would in normal operation. if the battery is removed during condi- tioning mode, the pds switch is turned back on and the system is powered from the ac adapter. ii vv v v rms chg batt dcin batt dcin = ? ? ? ? ? ? ? ? ? () 0 1.0 0.5 1.5 8 10111213 9 1415161718 v batt (v) ripple current (a) l = 10 h v dcin = 19v charge current = 3a 3 cells (12.6v) 4 cells (16.8v) figure 16. ripple current vs. battery voltage
MAX1535 highly integrated level 2 smbus battery charger 36 ______________________________________________________________________________________ setting input current limit the input current limit should be set based on the cur- rent capability of the ac adapter and the tolerance of the input current limit. the upper limit of the input cur- rent threshold should never exceed the adapter s mini- mum available output current. for example, if the adapter s output current rating is 5a 10%, the input current limit should be selected so that its upper limit is less than 5a 0.9 = 4.5a. since the input current-limit accuracy of the MAX1535 is 5%, the typical value of the input current limit should be set at 4.5a / 1.05 4.28a. the lower limit for input current must also be considered. for chargers at the low end of the specifi- cation, the input current limit for this example could be 4.28a 0.95, or approximately 4.07a. setting vmax and imax limits the vmax and imax limits should be determined based on the design values of the maximum current and voltage in the battery and the accuracy of vmax and imax limits. the vmax function is intended to be a secondary protection mechanism. so it is not relevant whether smbus or vmax controls the charger, so long as the charge voltage is below the battery manufactur- er s maximum ratings. the smbus and vmax thresh- olds can therefore overlap slightly because charge- voltage accuracy is critical for safely and efficiently charging the battery. the lower limit of the vmax threshold should be equal to the normal charge voltage of 4.20v per cell. assuming the accuracy of the vmax threshold is 5%, the typical value of the vmax limit should be set at 4.20 / 0.95 = 4.42v per cell. for a 4- cell battery pack, the nominal vmax limit is 4 4.42v = 17.68v. the accuracy of the charge current is not as critical as the charge voltage. small variations (such as 5%) in the absolute value of the charge current do not have a significant effect on the total charge time. it is accept- able to have the maximum charge current set by smbus and the imax limit overlap slightly. assuming the maximum charge current is 5a 5% and the accu- racy of the imax threshold is 5%, the lower limit of the imax threshold can be set equal to the upper limit of the maximum charge current (5.25a), or slightly lower. therefore, the typical value of the imax limit should be 5.25a / 0.95 = 5.53a, or slightly lower. layout and bypassing bypass dcin with a 1f ceramic capacitor to ground (figure 1). d4 protects the MAX1535 when the dc power source input is reversed. a signal diode for d4 is adequate because dcin only powers the ldo and the internal reference. bypass v dd , dcin, ldo, dhiv, dlov, src, dac, and ref as shown in figure 1. good pc board layout is required to achieve specified noise immunity, efficiency, and stable performance. the pc board layout artist must be given explicit instructions preferably a sketch showing the place- ment of the power-switching components and high-cur- rent routing. refer to the pc board layout in the MAX1535 evaluation kit for examples. a ground plane is essential for optimum performance. in most applica- tions, the circuit is located on a multilayer board, and full use of the four or more copper layers is recom- mended. use the top layer for high-current connec- tions, the bottom layer for quiet connections, and the inner layers for uninterrupted ground planes. system host (keyboard controller) smbus control signals for battery smbus control signals for battery system power supplies ac-to-dc converter (adapter) smart battery MAX1535 smart-battery charger/ power-source selector batt+ batt- ac line figure 17. typical smart-battery system
MAX1535 highly integrated level 2 smbus battery charger ______________________________________________________________________________________ 37 use the following step-by-step guide: 1) place the high-power connections first, with their grounds adjacent: minimize the current-sense resistor trace lengths, and ensure accurate current sensing with kelvin connections. minimize ground trace lengths in the high-current paths. minimize other trace lengths in the high-current paths. use >5mm wide traces in the high-current paths. connect c1 and c2 to the high-side mosfet (10mm, max length). minimize the lx node (mosfets, rectifier cathode, inductor (15mm, max length)). ideally, surface-mount power components are flush against each other with their ground terminals almost touching. these high-current grounds are then connected to each other with a wide, filled zone of top-layer copper, so they do not go through vias. the resulting top-layer subground plane is con- nected to the normal inner-layer ground plane at the output ground terminals, which ensures that the ic s analog ground is sensing at the supply s output ter- minals without interference from ir drops and ground noise. other high-current paths should also be minimized, but focusing primarily on short ground and current-sense connections eliminates about 90% of all pc board layout problems. 2) place the ic and signal components. keep the main switching node (lx node) away from sensitive analog components (current-sense traces and the ref capacitor). important : the ic must be no further than 10mm from the current-sense resistors. quiet con- nections to ref, vmax, imax, ccv, cci, ccs, acin, and dcin should be returned to a separate ground (gnd) island. the appropriate traces are marked on the schematic with the ground symbol . there is very little current flowing in these traces, so the ground island need not be very large. when placed on an inner layer, a sizable ground island can help simplify the layout because the low-current connec- tions can be made through vias. the ground pad on the backside of the package should also be con- nected to this quiet ground island. 3) keep the gate drive traces (dhi and dlo) as short as possible (l < 20mm), and route them away from the current-sense lines and ref. these traces should also be relatively wide (w > 1.25mm). 4) place ceramic bypass capacitors close to the ic. the bulk capacitors can be placed further away. place the current-sense input filter capacitors under the part, connected directly to the gnd pin. 5) use a single-point star ground placed directly below the part at the pgnd pin. connect the power ground (ground plane) and the quiet ground island at this location. see figure 18 for a layout example. chip information transistor count: 11,900 process: bicmos ( )
MAX1535 highly integrated level 2 smbus battery charger 38 ______________________________________________________________________________________ inductor c in c out c out input output kelvin-sense vias under the sense resistor (refer to evaluation kit) gnd via connecting power ground to quiet analog ground high-current pgnd plane quiet gnd island figure 18. MAX1535 pc board layout example
MAX1535 highly integrated level 2 smbus battery charger maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 39 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) qfn thin.eps d2 (nd-1) x e e d c pin # 1 i.d. (ne-1) x e e/2 e 0.08 c 0.10 c a a1 a3 detail a 0.15 c b 0.15 c a document control no. 21-0140 package outline 16, 20, 28, 32l, qfn thin, 5x5x0.8 mm proprietary information approval title: c rev. 2 1 e2/2 e2 0.10 m c a b pin # 1 i.d. b 0.35x45 l d/2 d2/2 l c l c e e l cc l k k l l 2 2 21-0140 rev. document control no. approval proprietary information title: common dimensions exposed pad variations 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220. notes: 10. warpage shall not exceed 0.10 mm. c package outline 16, 20, 28, 32l, qfn thin, 5x5x0.8 mm

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